• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A digital finite impulse response (FIR) filter is provided in which a plurality of weighted signal taps are symmetrically located in time about a weighted center tap. Weighted signals from the symmetrically located taps are summed at a first point in the filter, which sum is then combined with signals from the center tap in one sense, that is, either additively or subtractively, to produce signals at a first output. The summed signals at the first point are also combined with signals from the center tap in an opposite sense to produce signals at a second output. The two outputs will exhibit bandpass and lowpass filter response characteristics, with the outputs at which the respective responses are produced being determined by the respective senses of signal combination. The FIR filter may be of either the input tap-weighted or output tap-weighted variety.
    公开号:SU1313362A3
    申请号:SU823509653
    申请日:1982-11-04
    公开日:1987-05-23
    发明作者:Анкапора Альфонс
    申请人:Рка Корпорейшн (Фирма)；
    IPC主号:
    专利说明:

    one
    The invention relates to computing, in particular, to a digital filter providing two output signals at its outputs exhibiting different frequency characteristics with respect to the input signal.
    The purpose of the invention is to simplify the filter.
    Fig, 1 is a block diagram of a digital filter; FIGS. 2-4 show frequency response curves.
    The digital filter (fig, 1) contains shift registers 1--21, adders 22-30, blocks 31 and 32 elements NOT,
    The digital filter works as follows.
    Since the weighting function coefficients have different powers of the number 2 in the denominator, the signals from the taps can be weighed using the shift and sum method, which eliminates the need for multiplying the coefficients. Since, for example, the values of the weighting factors for the ninth and thirteenth shift registers are equal to (5/16), these two signals can be summed up in the adder 22 before weighting. If the length of each signal is equal to eight bits, then the output of the adder 22 is nine-bit the words of the Dev two-bit output signal of the adder 22 is divided into sixteen and four when the adder 22 is connected to the inputs of the adder 25, corresponding to the switching of bits,
    Similarly, the signals removed from the fifth and seventeenth shift registers are summed in adder 23, which produces a nine-bit output signal. The output signal of the adder 23 is divided into sixty four and sixteen when it is fed to the two inputs of the adder.
    The adder 26 produces a six-bit output signal j which is weighted at (5/64) with respect to the signals at the register outputs. This output signal is inverted by the block 31 of the elements NOT and is fed to the input of the adder 29 together with the logical 1 bit of the input. The inverse of the signal and the bit of the input perform the formation of an addition to the two output bits of the adder 26, which in binary arithmetic provides
    622
    minus sign before the weighting factor.
    Signals taken from the first and twenty first shift registers,
    summed in the adder 24, the output of which is divided into sixty four by supplying the three most significant output bits of the adder 24 to the second input of the adder 29, Exit
    the latter is connected to one input of the adder 22, and the output of the adder 25 is connected to another input of the adder 28, the latter produces an output signal which is
    the sum of the weighted signals from all the shift registers except the central eleventh.
    The output of the adder 28 is connected to one of the inputs of the adder 27 ,. The other input of which is fed to the seven most significant bits of the signal removed from the central eleventh register. As a result, the output of the adder 27 has a low-pass filter characteristic.
    The seven most significant bits of the signal removed from the central eleventh register are fed to the corresponding input of the adder 30, the output of the adder 28 is connected to another input of the adder 30 through a block of 32 elements NOT with the logical 1 bit of the input. Inversion of the output signal of the adder 28 along with.
    the row of input ensures the formation of an addition to the two output signal of the adder 28; As a result, in the adder 30, the output signal of the adder 28 is subtracted from the
    signal from the central register, at the output of the adder 30 there is a frequency response of the band-pass filter.
    45
    权利要求:
    Claims (1)
    [1]
    Invention Formula
    A digital filter containing first through twenty-first serially connected shift registers Q ry from first to nine adders, the output of the first adder connected to the first input of the second adder, the output of which is connected to the first input of the third adder,
    .j whose output is the output of the first frequency component of the filter, whose information input is the information input of the first shift register, distinguished by 313
    Yi and with the fact that, for the purpose of simplification, it contains the first and second blocks of elements NOT, with the outputs of the ninth and thirteenth shift registers connected to the first and second inputs of the fourth adder, the outputs i-ro (, M; M- bit) d) and j-ro (, M) bits of which are connected respectively to (1-4) -th bit of the first input and (j-2) -My bit of the second input of the fifth adder, the output of which is connected to the second input of the second adder, the output of which is connected to the input of the first block of elements NOT, the output of which is connected to the first input the adder, the output of which is the output of the second frequency component of the filter, the outputs of the fifth and seventeenth shift registers
    362 .4
    are connected respectively to the first and second inputs of the seventh adder, the outputs of the K-th () and i-ro bits of which are connected respectively to
    5 (KB) -th bit of the first input and (1-A) -th bit of the second input of the eighth adder, the output of which is connected to the input of the second block of elements NOT, the output of which is connected to
    10 the first input of the first adder,
    (KB) -th bit of the second input of which is connected to the output of the K-th bit of the ninth adder, the first and second inputs of which are connected to the outputs
    15, respectively, of the first and twenty-first shift registers, the output of the 1st (, M) bit of the eleventh shift register is connected to (1-1) -th bit of the second inputs of the third 0 of its sixth adders.
    0,
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    US4096516A|1977-03-25|1978-06-20|Rca Corporation|Electronic signal processing apparatus|
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    GB2022954B|1978-03-30|1982-04-07|Secr Defence|Transversal filters|
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    法律状态:
    优先权:
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